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19-4000; Rev 1; 4/09
High-Voltage Watchdog Timers with Adjustable Timeout Delay
General Description
The MAX16997/MAX16998 are microprocessor (P) supervisory circuits for high-input-voltage and low-quiescent-current applications. These devices detect downstream circuit failures and provide switchover to redundant circuitry. See the Selector Guide for the different versions of this product family. The MAX16997/MAX16998 family has four independent inputs for reset and watchdog functions. SWT and SRT inputs independently set the timeout periods of watchdog and reset timers through external capacitors. RESETIN/EN monitor voltages at respective inputs. A resistive voltage-divider sets the reset threshold. The MAX16998A/B/D generate two output signals, RESET and ENABLE. RESET asserts whenever RESETIN drops below its threshold voltage or when the watchdog timer detects a timing fault at WDI. Once asserted, and after all reset conditions are removed, RESET remains low for the reset timeout period, tRESET, and then goes high. The MAX16997A generates one output signal (ENABLE) based on the voltage level at EN and the signal at WDI. The MAX16997A does not have a RESET output. The watchdog is disabled if the voltage at EN is below its threshold. The MAX16997A watchdog timer starts timing when the voltage at EN becomes higher than the preset threshold voltage level. Each time EN rises above the preset threshold voltage, the initial watchdog timeout period is 8 times the normal watchdog timeout period (tWP). The MAX16997/MAX16998 are available in 8-pin leadfree MAX(R) packages and are fully specified over the -40C to +125C automotive temperature range. o Wide 5V to 40V Input Voltage Range o 18A Quiescent Current (Typical at +125C) o Capacitor-Adjustable Timeout Period for Watchdog and Reset o Windowed Watchdog Timer Options (MAX16998B/D) o External Voltage Monitoring (RESETIN for the MAX16998A/B/D and EN for the MAX16997A) o Car Battery-Compatible EN Input o TTL- and CMOS-Compatible Open-Drain Outputs o 18V Maximum Open-Drain Reset Output Voltage o 28V Maximum Open-Drain Enable Output Voltage o Power-On/Power-Off Reset Functionality (MAX16998A/B/D Only) o AECQ-100 Qualified o -40C to +125C Operating Temperature Range o Small (3mm x 3mm) MAX Package o WDI Narrow Pulse Immunity
Features
MAX16997/MAX16998
Ordering Information
PART MAX16997AAUA+ MAX16998AAUA+ MAX16998BAUA+ MAX16998DAUA+ TEMP RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C PIN-PACKAGE 8 MAX 8 MAX 8 MAX 8 MAX
Applications
Automotive Industrial
+Denotes a lead(Pb)-free/RoHS-compliant package.
Selector Guide
PART MAX16997A MAX16998A MAX16998B MAX16998D WATCHDOG WINDOW SIZE (%) 100 100 50 75 ENABLE RESET -- EN -- -- -- RESETIN --
Pin Configurations appear at end of data sheet. MAX is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
High-Voltage Watchdog Timers with Adjustable Timeout Delay MAX16997/MAX16998
ABSOLUTE MAXIMUM RATINGS
(All pins referenced to GND, unless otherwise noted.) IN, ENABLE ............................................................-0.3V to +45V WDI, RESET, EN .....................................................-0.3V to +20V RESETIN .................................................................-0.3V to +20V SRT, SWT................................................................-0.3V to +12V Maximum Current (all pins).................................................30mA Continuous Power Dissipation (TA = +70C) 8-Pin MAX (derate 4.8mW/C above +70C) ..........387.8mW Junction-to-Case Thermal Resistance (JC) (Note 1) ......42C/W Junction-to-Ambient Thermal Resistance (JA ) (Note 1).....206.3C/W Operating Temperature Range (TA) ..................-40C to +125C Junction Temperature (TJ) ...............................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 14V, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Operating Voltage Range Supply Current SWT Ramp Current SRT Ramp Current SWT/SRT Ramp Threshold Voltage RESET TIMER Power-On Reset Input Threshold Voltage RESETIN Input Leakage Current RESET Output Low Voltage RESET Leakage Current ENABLE Output Low Voltage ENABLE Leakage Current Minimum Reset Timeout Period Reset Timeout Period Maximum Reset Time Period RESET to ENABLE Delay RESETIN to RESET Delay VPON ILPON VOLRST ILKGR VOLEN ILKGE tRESETmin tRESET tRESETmax tREDL tRRDL RESETIN falling below VPON to RESET falling edge VRESETIN rising VRESETIN falling VRESETIN = 2V RESET asserted, ISINK = 1mA VIN = 1.1V, ISINK = 160A, RESET asserted RESET asserted, ISINK = 0.4mA VRESET = 20V, RESET not asserted ENABLE asserted, ISINK = 5mA VENABLE = 14V, ENABLE not asserted CSRT = 390pF (Note 3) CSRT = 2000pF (Note 3) CSRT = 47nF 0.1 1 5 116.09 1.5 1 0.1 0.4 1.135 1.115 1.255 1.235 0.1 0.9 0.4 0.4 A V A ms ms ms s s V 1.383 1.363 V A SYMBOL VIN IIN TA = -40C to +85C TA = -40C to +125C 450 410 1.115 CONDITIONS MIN 5.0 18 18 500 500 1.235 TYP MAX 40.0 30 60 550 600 1.363 UNITS V A nA nA V
IRAMP_SWT VSWT = 1.0V IRAMP_SRT VSRT = 1.0V VRAMP
2
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High-Voltage Watchdog Timers with Adjustable Timeout Delay
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 14V, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER WATCHDOG TIMER WDI Input Threshold WDI Input Hysteresis WDI Minimum Pulse Width WDI Input Current Minimum Watchdog Timeout Watchdog Timeout Period Maximum Watchdog Timeout Watchdog Window WDI to ENABLE Output Delay RESET Pullup Resistor Supply Voltage ENABLE Pullup Resistor Supply Voltage VIH VIL WDIHYST tWDImin IWDI tWPmin tWP tWPmax DWDI (Note 4) WDI = 0 or 14V CSWT = 680pF (Note 3) CSWT = 1200pF (Note 3) CSWT = 22nF MAX16998B MAX16998D Start from WDI third wrong trigger (Note 5) 2.25 45 67.5 6.5 0.1 6.8 12 217.36 50 75 100 2.5 18.00 55 82.5 200 2.25 0.9 V mV s A ms ms ms %tWP s V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX16997/MAX16998
(Note 5)
2.25
2.5
28.00
V
Note 2: RRESET and RENABLE are external pullup resistors for open-drain outputs. Connect RRESET and RENABLE to a minimum 2.5V voltage. Connect RRESET to a maximum voltage of 18V and connect RENABLE to a maximum voltage of 28V. Note 3: Calculated based on VRAMP = 1.235V and IRAMP = 500nA. Note 4: WDI pulses narrower than 1s will be ignored. WDI pulses wider than 6.5s will be recognized. Note 5: Not production tested, guaranteed by design.
Typical Operating Characteristics
(CSWT = CSRT = 1500pF, TA = +25C, unless otherwise noted.)
RESET TIMEOUT PERIOD vs. CSRT
MAX16997/98 toc01
WATCHDOG TIMEOUT PERIOD vs. CSWT
MAX16997/98 toc02
SUPPLY CURRENT vs. SUPPLY VOLTAGE
24 SUPPLY CURRENT (A) 22 20 18 16 14 12 RESET AND ENABLE NOT ASSERTED
MAX16997/98 toc03
10,000
IRAMP = 500nA
10,000 WATCHDOG TIMEOUT PERIOD (ms)
IRAMP = 500nA
26
RESET TIMEOUT PERIOD (ms)
1000
1000
100
100
10
10
1
0.1 0.1 1 10 CSRT (nF) 100 1000
1 0.1 1 10 CSWT (nF) 100 1000
10 0 10 20 30 40 50 SUPPLY VOLTAGE (V)
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3
High-Voltage Watchdog Timers with Adjustable Timeout Delay MAX16997/MAX16998
Typical Operating Characteristics (continued)
(CSWT = CSRT = 1500pF, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX16997/98 toc04
RESETIN/EN THRESHOLD VOLTAGE vs. TEMPERATURE
MAX16997/98 toc05
RESETIN/EN THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE
RESETIN/EN THRESHOLD VOLTAGE (V) 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 FALLING RISING
MAX16997/98 toc06
20.0 19.5 19.0 SUPPLY CURRENT (A) 18.5 18.0 17.5 17.0 16.5 16.0 15.5 15.0 RESET AND ENABLE NOT ASSERTED
1.35 RESETIN/EN THRESHOLD VOLTAGE (V) 1.33 1.30 1.28 1.25 1.23 1.20 1.18 1.15 1.13 1.10 FALLING RISING
1.50
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
4
8
12
16
20
24
28
32
36
40
SUPPLY VOLTAGE (V)
RESETIN TO RESET DELAY vs. TEMPERATURE
MAX16997/98 toc07
RESETIN/WATCHDOG PERIOD vs. SUPPLY VOLTAGE
MAX16997/98 toc08
RESETIN/WATCHDOG PERIOD vs. SUPPLY VOLTAGE
RESET/WATCHDOG TIMEOUT PERIOD (ms) 100 90 80 70 60 50 40 30 20 10 4 8 12 16 20 24 28 32 36 40 RESET TIMEOUT PERIOD (CSRT = 10nF) WATCHDOG TIMEOUT PERIOD (CSWT = 10nF)
MAX16997/98 toc09
2.00 1.75 RESETIN TO RESET DELAY (s) 1.50 1.25 1.00 0.75 0.50 0.25 0 50mV OVERDRIVE 100mV OVERDRIVE RESETIN FROM 2V TO 0V
8 RESET/WATCHDOG TIMEOUT PERIOD (ms) 7 6 5 4 3 2 1 0 4 8 12 16 20 24 28 32 36 RESET TIMEOUT PERIOD (CSRT = 680pF) WATCHDOG TIMEOUT PERIOD (CSWT = 680pF)
110
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
40
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
IRAMP vs. TEMPERATURE
MAX16997/98 toc10
RESET OUTPUT VOLTAGE vs. SINK CURRENT
0.9 RESET OUTPUT VOLTAGE (V) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
MAX16997/98 toc11
ENABLE OUTPUT VOLTAGE vs. SINK CURRENT
0.7 ENABLE OUTPUT VOLTAGE (V) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 5 10 15 20 25 30
MAX16997/98 toc12
520 515 510 505 IRAMP (nA) 500 495 490 485 480 475 470
1.0
0.8
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
0
0.5
1.0
1.5
2.0
2.5
3.0
SINK CURRENT (mA)
SINK CURRENT (mA)
4
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High-Voltage Watchdog Timers with Adjustable Timeout Delay
Pin Description
PIN MAX16997A 1 2 3, 7 MAX16998A/B/D 1 -- -- NAME IN EN N.C. FUNCTION Power-Supply Input. Bypass IN to GND with a 0.1F capacitor. High-Impedance Input to the Enable Comparator. Depending on the voltage level at EN, the internal watchdog timer is turned on or off (see the EN Input section). No Connection. Not internally connected. Watchdog Timeout Adjustment Input. Connect a capacitor between SWT and GND to set the basic watchdog timeout period. Connect SWT to ground to disable the watchdog timer function. See the Selecting the Watchdog Timeout Capacitor section. Ground Watchdog Input. MAX16997A/MAX16998A (Timeout Watchdog): Two consecutive WDI falling edges must occur at WDI within the watchdog timeout period or RESET asserts. The watchdog timer clears when a falling edge occurs on WDI or whenever RESET is asserted. ENABLE asserts if three consecutive watchdog timeout periods have expired without a falling edge at WDI. WDI is a high-impedance input. Leaving WDI unconnected will cause improper operation of the watchdog timer. MAX16998B/D (Window Watchdog): WDI falling transitions within periods shorter than the closed window width or longer than the basic watchdog timeout period force RESET to assert low for the reset timeout period. The watchdog timer begins to count after RESET is deasserted. The watchdog timer clears when a WDI falling edge occurs or whenever RESET is asserted. ENABLE asserts if three consecutive watchdog timeout periods have expired without a falling edge at WDI. WDI is a high-impedance input. Leaving WDI unconnected will cause improper operation of the watchdog timer. Open-Drain Enable Output. ENABLE asserts when three consecutive WDI faults occur. ENABLE remains low until three consecutive good WDI falling edges occur. ENABLE does not assert if the voltage at RESETIN (EN) is below its threshold. These devices are guaranteed to be in correct ENABLE output logic state when VIN remains greater than 1.1V. Reset Input. High-impedance input to the reset comparator. When VRESETIN falls below 1.235V, RESET asserts. RESET remains asserted as long as VRESETIN is low and for the reset timeout period after RESETIN goes high. Connect VRESETIN to the center point of an external resistive divider to set the threshold for the externally monitored voltage. Connect RESETIN to a defined voltage logic-level. Reset Timeout Adjustment Input. Connect a capacitor between SRT and GND to set the reset timeout period. See the Selecting the Reset Timeout Capacitor section. Open-Drain Reset Output. RESET asserts whenever RESETIN drops below the selected reset threshold voltage (VPON). RESET remains low for the reset timeout period after all reset conditions are removed, and then goes high. RESET asserts for a period of tRESET whenever a WDI fault occurs. Connect RESET to a pullup resistor connected to a voltage higher than 2.5V (typ).
MAX16997/MAX16998
4
4
SWT
5
5
GND
6
6
WDI
8
8
ENABLE
--
2
RESETIN
--
3
SRT
--
7
RESET
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5
High-Voltage Watchdog Timers with Adjustable Timeout Delay MAX16997/MAX16998
Functional Diagram
IN
MAX16997/MAX16998
PREG RESET
RESETIN (MAX16998) EN (MAX16997)
VBG
WDI
BUFFER MAX16997A/ MAX16998A/B/D LOGIC VBG
ENABLE
IRAMP
SRT (MAX16998)
IRAMP VBG SWT
GND
6
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High-Voltage Watchdog Timers with Adjustable Timeout Delay
Timing Diagrams
VEN VHYST VPON tWP tWD tWP INITIAL WDI 1 2 3 1 2 3 tWDI tWP tWP tWP tWP tWDI tWDI tWDI
MAX16997/MAX16998
ENABLE
tWP INITIAL = WATCHDOG TIMEOUT PERIOD x 8
tWP = WATCHDOG TIMEOUT PERIOD
tWDI = WDI TRIGGER PERIOD
3 CONSECUTIVE tWP WITHOUT TRIGGER ENABLE GOES LOW
3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH
Figure 1. MAX16997A Timing Diagram
VRESETIN VHYST VPON
tRESET WDI tWP
tWDI
tWP
tWP
tWP
tWDI
tWDI
tWDI
1
2
3
RESET ENABLE
1
2
3
tRESET = RESET TIMEOUT PERIOD
tWP = WATCHDOG TIMEOUT PERIOD
tWDI = WDI TRIGGER PERIOD
3 CONSECUTIVE RESETS ENABLE GOES ACTIVE LOW
3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH
Figure 2. MAX16998A Timing Diagram
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High-Voltage Watchdog Timers with Adjustable Timeout Delay MAX16997/MAX16998
Timing Diagrams (continued)
VRESETIN VPON
VHYST
PROPER WATCHDOG TRIGGER RESETS THE INTERNAL ENABLE COUNTER tRESET WDI tWP tOW tWDI tCW tWP tWP tWP tWDI tWDI tWDI
1
2
3
1 RESET ENABLE
2
3
tRESET = RESET TIMEOUT PERIOD
tOW = T OPEN WINDOW
tCW = T CLOSED WINDOW
tWP = tCW + tOW
tWDI = WDI TRIGGER PERIOD
3 CONSECUTIVE RESETS ENABLE GOES ACTIVE LOW
3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH
Figure 3. MAX16998B/D Timing Diagram
VRESETIN VPON tRESET tRRDL RESET VHYST tRESET tRESET
VIN = ENABLE 1.1V WDI tCW tWDI tWP tWDI tWDI tWDI tWDI tWDI tWDI ENABLE DOES NOT GET ASSERTED IF THE VOLTAGE AT RESETIN IS BELOW ITS THRESHOLD.
tWP
tWDI tWDI
tCW
tWP
THE WATCHDOG TIMER CLEARS WHENEVER RESET IS ASSERTED.
tCW tWDI tWP
t=0
tOW
Figure 4. RESETIN, RESET, VIN, ENABLE, and WDI Voltage Monitoring
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High-Voltage Watchdog Timers with Adjustable Timeout Delay
Detailed Description
The MAX16997/MAX16998 are P supervisory circuits for high-input-voltage and low-quiescent-current applications. These devices improve system reliability by monitoring the sub-system for software code execution errors. The MAX16997A/MAX16998A/B/D detect downstream circuit failures, and provide switchover to redundant circuitry. These devices provide complete adjustability for reset and watchdog functions. The MAX16998A/B/D generate two output signals, RESET and ENABLE, that depend on the voltage level at RESETIN and the signal at WDI. RESET asserts whenever RESETIN drops below the selected reset threshold voltage. RESET remains low for the reset timeout period after all reset conditions are deasserted, and then goes high. RESET also asserts for a period of tRESET whenever a WDI fault occurs. The MAX16997A generates one output signal (ENABLE) based on the voltage level at EN and the signal at WDI. The MAX16997A/MAX16998A provide watchdog timeout adjustability with an external capacitor. The MAX16998A asserts RESET when two consecutive WDI falling edges do not occur within the watchdog timeout period. This device also asserts ENABLE if three consecutive watchdog timeout periods have elapsed without a falling edge at WDI. ENABLE remains low until three consecutive good WDI falling edges occur. ENABLE does not assert if the voltage at RESETIN (EN) is below its threshold. For the MAX16997A, the watchdog timer starts timing if the voltage at EN is higher than a preset threshold level. Each time the voltage at EN rises from below to above the preset threshold voltage, the initial watchdog timeout period is 8 times the normal watchdog timeout period (t WP ). Other than described above, the MAX16997A behaves the same as the MAX16998A. The MAX16998B/MAX16998D contain a window watchdog timer that looks for activity outside an expected window of operation. The window size is factory-set to 50% (MAX16998B) or 75% (MAX16998D) of the adjusted watchdog timeout period. For the MAX16998A/B/D, RESET asserts whenever RESETIN drops below the selected reset threshold voltage (VPON). RESET remains low for the reset timeout period after RESETIN exceeds the selected threshold voltage, and then goes high. The MAX16998A asserts RESET for a period of tRESET when two consecutive WDI falling edges do not occur within the adjusted watchdog timeout period. The MAX16998B/D also assert RESET for a period of tRESET when a WDI falling edge does not occur within the open window period. Anytime reset asserts, the watchdog timer clears. At the end of the reset timeout period, RESET goes high, and the watchdog timer is restarted from zero (see the Selecting the Watchdog Timeout Capacitor section).
MAX16997/MAX16998
Enable Output (ENABLE)
If the C fails to operate correctly (e.g., the software execution is stuck in a loop), WDI does not trigger any more and RESET pulls low, resetting the C. If the C does not work properly in the next loop either, the device asserts RESET again. After three watchdog timeout periods elapse with no falling edges at WDI, ENABLE asserts and flags a backup circuit that can take over the operation. ENABLE remains low until three consecutive WDI falling edges with periods shorter than the watchdog timeout occur. ENABLE does not assert if the voltage at RESETIN (EN) is below its threshold. These devices are guaranteed to be in correct ENABLE output logic state when VIN remains greater than 1.1V.
Power-On/Power-Off Sequence
Figure 5 shows the power-up and power-down sequence for RESET and ENABLE for the MAX16998A/B/D. On power-up, once V IN reaches 1.1V, RESET goes logic-low. As RESETIN rises, RESET remains low. When RESETIN rises above VPON, the reset timer starts and RESET remains low. When the reset timeout period ends, RESET goes high. On power-down, once RESETIN goes below V PON , RESET goes low and remains low until VIN drops below 1.1V. Figure 6 shows the detailed power-up sequence for the MAX16998A/B/D.
Reset Output (RESET) (MAX16998A/B/D)
The reset output is typically connected to the reset input of the C to start or restart it in a known state. The MAX16998A/B/D provide an active-low open-drain reset logic to prevent code execution errors.
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9
High-Voltage Watchdog Timers with Adjustable Timeout Delay MAX16997/MAX16998
VIN VIN = 1.1V
VRESETIN VHYST VPON tRESET RESET tRESET tRESET tRESET
ENABLE tCW tWDI tWP WDI tWDI tWDI tWDI tWDI tWDI tWDI
tWP
tWP
tWP
tWDI tWDI THE THREE CONSECUTIVE RESET COULD BE CAUSED BY THREE TIMEOUTS AS SHOWN HERE OR BY THREE WDI FALLING EDGE OUTSIDE THE OPEN WINDOW, OR A COMBINATION OF ANY RESET CONDITIONS EXCEPT VRESETIN DROPS TOO LOW.
tCW tWDI tWP
tCW tOW t=0
tWP
WDI WDT CLEARS AND STARTS COUNTING FROM O
RESET
Figure 5. Power-On Reset and Power-Down Reset for the MAX16998A/B/D
VIN = VENABLE VIN = 1.1V
VPON
VHYST
VRESETIN
tRESET VRESET
Figure 6. Detailed Power-Up Sequence for the MAX16998A/B/D
10 ______________________________________________________________________________________
High-Voltage Watchdog Timers with Adjustable Timeout Delay
RESETIN Input (MAX16998A/B/D)
The MAX16998A/B/D monitor the voltage at RESETIN using an adjustable reset threshold, set with an external resistive divider (see Figure 7). RESET asserts when VRESETIN is below 1.235V. Use the following equations to calculate the externally monitored voltage (VCC). R VTH = VPON 1 + 1 R2 where VTH is the desired reset threshold voltage, and V PON = 1.235V. To simplify the resistor selection, choose a value for R2 (< than 1M) and calculate R1. V R1 = R2 TH - 1 VPON
VCC
MAX16997/MAX16998
VIN
MAX16998A/B/D
R1 RESETIN R2
Figure 7. Setting RESETIN Voltage for the MAX16998A/B/D
EN Input
The MAX16997A provides a high-impedance input (EN) to the enable comparator. Based on the voltage level at EN, the watchdog timer is turned on or off. The watchdog timer starts timing if the voltage level at EN is higher than a preset threshold voltage (VPON). Each time the voltage at EN rises from below to above the preset threshold voltage, the initial watchdog timeout period is 8 times the normal watchdog timeout period (tWP).
Watchdog Timer
MAX16997A The watchdog circuit monitors the C's activity. For the MAX16997A, the watchdog timer starts timing once the voltage at EN is higher than a preset threshold voltage. ENABLE asserts if three consecutive watchdog timeout periods have elapsed without a falling edge at WDI. ENABLE remains low until three consecutive WDI falling edges with periods shorter than the watchdog timeout period occur. Each time the voltage at EN rises from below to above the preset threshold voltage, the first watchdog timeout period extends by a factor of 8 (8 x tWP). If a WDI falling edge occurs during that time, then the watchdog timeout period is immediately switched over to a single tWP. If no watchdog falling edge occurs during this prolonged watchdog timeout period, ENABLE goes low at the end of this period and stays low. After this, the first falling edge at WDI switches the watchdog timeout period to a single tWP. See Figure 1. The MAX16997A watchdog timeout period (tWP) is adjustable by a single capacitor at SWT.
MAX16998A The MAX16998A asserts RESET when two consecutive WDI falling edges do not occur within the adjusted watchdog timeout period (tWP). RESET remains asserted for the reset timeout period (tRESET) and then goes high. This device also asserts ENABLE if three consecutive watchdog timeout periods have elapsed without a falling edge at WDI. ENABLE remains low until three consecutive WDI falling edges with periods shorter than the watchdog timeout period occur (see Figure 2). The internal watchdog timer is cleared by a RESET rising edge or by a falling edge at WDI. The watchdog timer remains cleared while RESET is asserted; as soon as RESET is released, the timer starts counting. WDI falling edges are ignored when RESET is low. If no WDI falling edge occurs within the watchdog timeout period, RESET immediately goes low and stays low for the adjusted reset timeout period. MAX16998B/D The MAX16998B/D have a windowed watchdog timer. The watchdog timeout period (t WP ) is the sum of a closed window period (tCW) and an open window period (tOW). If the C issues a WDI falling edge within the open window period, RESET stays high. Once a WDI falling edge occurs within the closed window period, RESET immediately goes low and stays low for the adjusted reset timeout period (see Figure 3). If no WDI falling edge occurs within the watchdog timeout period, RESET immediately goes low and stays low for the adjusted reset timeout period. The open window size is factory-set to 50% of the watchdog timeout period for the MAX16998B and 75% for the MAX16998D. Figure 8 shows a WDI falling edge identified as a good or a bad WDI signal edge. In case 1, the WDI falling edge occurs within the closed window period and is considered a bad WDI falling edge (early fault); therefore, it asserts RESET. Case 2 also shows another fault. In this case, no
11
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High-Voltage Watchdog Timers with Adjustable Timeout Delay MAX16997/MAX16998
WDI falling edge occurs within the watchdog timeout period (tWP) and is considered a late fault that asserts RESET. In case 3, the WDI falling edge occurs within the open window period and is considered a good WDI signal falling edge. In this case, RESET stays high. In case 4, the WDI falling edge occurs within the indeterminate region. In this case, the RESET state is indeterminate. These devices assert ENABLE after three consecutive bad WDI falling edges. ENABLE returns high after three consecutive good WDI signal falling edges (see Figure 3). Either a rising edge at RESET or a falling edge at WDI clears the internal watchdog timer. The watchdog timer remains cleared while RESET is asserted. The watchdog timer begins counting when RESET goes high. WDI falling edges are ignored when RESET is low. Leakage currents and stray capacitance (e.g., a scope probe, which induces both) at SRT may cause errors in the reset timeout period. If precise time control is required, use capacitors with low leakage current and high stability.
Selecting the Watchdog Timeout Capacitor
The watchdog timeout period is adjustable to accommodate a variety of P applications. With this feature, the watchdog timeout can be optimized for software execution. The programmer determines how often the watchdog timer should be serviced. Adjust the watchdog timeout period (tWP) by connecting a capacitor (C SWT ) between SWT and GND. For normal mode operation, calculate the watchdog timeout capacitance using the following equation: CSWT = t WP x IRAMP 4 x VRAMP
Applications Information
Selecting the Reset Timeout Capacitor
The reset timeout period is adjustable to accommodate a variety of P applications. Adjust the reset timeout period (tRESET) by connecting a capacitor (CSRT) between SRT and ground. See the Reset Timeout Period vs. CSRT graph in the Typical Operating Characteristics. Calculate the reset timeout capacitance using the equation below: I CSRT = tRESET x RAMP VRAMP where VRAMP is in volts, tRESET is in seconds, IRAMP is in nA, and CSRT is in nF.
where VRAMP is in volts, tWP is in seconds, IRAMP is in nA, and CSWT is in nF. See the Watchdog Timeout Period vs. CSWT graph in the Typical Operating Characteristics. For the MAX16998B/MAX16998D, the open window size is factory-set to 50% (MAX16998B) or 75% (MAX16998D) of the watchdog period. Leakage currents and stray capacitance (e.g., a scope probe, which induces both) at SWT may cause errors in the watchdog timeout period. If precise time control is required, use capacitors with low leakage current and high stability. To disable the watchdog timer function, connect SWT to ground and connect WDI to either the high- or low-logic state.
tWP
RESET RISING EDGE
(50% or 75%) x tWP tWDImin tWDImax
CLOSED WINDOW
INDETERMINATE
OPEN WINDOW
CASE 1 (FAST FAULT)
CASE 2 (SLOW FAULT)
CASE 3 (GOOD WDI)
CASE 4 (INDETERMINATE)
Figure 8. The MAX16998B/D Window Watchdog Diagram
12 ______________________________________________________________________________________
High-Voltage Watchdog Timers with Adjustable Timeout Delay
Interfacing to Other Voltages for Logic Compatibility
As shown in Figure 9, the open-drain RESET output can operate in the 2.5V to 18V range. This allows the device to interface a P with other logic levels. RESETIN is a high-impedance input and a high-impedance resistive divider (e.g., 100k to 1M) sets the threshold level. Minimize coupling to transient signals by keeping the connections to this input short. Any DC leakage current at RESETIN (e.g., a scope probe) causes errors in the programmed reset threshold.
MAX16997/MAX16998
WDI Glitch Immunity
For additional glitch immunity, connect an RC lowpass filter as close as possible to WDI (see Figure 10). For example, for glitches with duration of 1s, a 12k resistor and a 47pF capacitor will provide immunity.
Typical Operating Circuits
RESET remains asserted as long as RESETIN is below the regulated voltage and for the reset timeout period after RESETIN goes high to assure that the monitored LDO voltage is settled. Then, the C starts operating and triggers WDI. If the C fails to operate correctly (e.g., the software execution is stuck in a loop), the WDI signal does not trigger the watchdog timer any more, and RESET is pulled low, resetting the C. If the C does not work properly in the next loop either, the device asserts RESET again. After three watchdog timeout periods with no WDI falling edges, ENABLE asserts and flags backup or safety circuits that take over the operation.
Layout Considerations
SRT and SWT are connected to internal precision current sources. When developing the layout for the application, minimize stray capacitance attached to SRT and SWT as well as leakage currents that can reach those nodes. SRT and SWT traces should be as short as possible. Route traces carrying high-speed digital signals and traces with large voltage potentials as far from SRT and SWT as possible. Leakage currents and stray capacitance (e.g., a scope probe, which induces both) at these pins may cause errors in the reset and/or watchdog timeout period. When evaluating these parts, use clean prototype boards to ensure accurate reset and watchdog timeout periods.
5V TO 40V IN 10k
2.5V TO 18V IN
MAX16998A/B/D
RESET
VCC RESET P
MAX16998A/B/D
VCC
R WDI C I/O P
N
GND
GND
GND
GND
Figure 9. Interfacing to Other Voltage Levels
Figure 10. Additional WDI Glitch Immunity Circuit
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13
High-Voltage Watchdog Timers with Adjustable Timeout Delay MAX16997/MAX16998
VBATT
IN SRT ENABLE VCC VCC EN BACKUP CIRCUITRY, PERIPHERAL 5V REGULATOR
MAX16998A/B/D
R1 RESET RESETIN C R2 SWT GND WDI I/O GND RESET
Figure 11. MAX16998A/B/D Switch Over to Backup Circuitry
VBATT BACKUP CIRCUITRY FLAGS ENABLE VCC 5V REGULATOR LDO BACKUP CIRCUITRY, PERIPHERAL
IN
MAX16997A
R1 EN R2 SWT WDI I/O
C RESET WATCHDOG I/O GND GND SEPARATE WATCHDOG 5V
Figure 12. MAX16997A Application Diagram
14
______________________________________________________________________________________
High-Voltage Watchdog Timers with Adjustable Timeout Delay
Pin Configurations
TOP VIEW
+ +
MAX16997/MAX16998
IN EN N.C. SWT
1 2 3 4
8 7
ENABLE N.C. WDI GND
IN RESETIN SRT SWT
1 2 3 4
8 7 6 5
ENABLE RESET WDI GND
MAX16997A
6 5
MAX16998A/B/D
MAX
MAX
Chip Information
PROCESS: BiCMOS
PACKAGE TYPE 8 MAX
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE CODE U8-1 DOCUMENT NO. 21-0036
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15
High-Voltage Watchdog Timers with Adjustable Timeout Delay MAX16997/MAX16998
Revision History
REVISION NUMBER 0 1 REVISION DATE 2/08 3/09 Initial release Added bullet to Features section, revised Electrical Characteristics table. DESCRIPTION PAGES CHANGED -- 1, 2, 3
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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